Related subject matter is disclosed in commonly-assigned, co-pending patent applications entitled xe2x80x9cUSE OF AN ETCH TO REDUCE THE THICKNESS AND ROUND THE EDGES OF A RESIST MASK DURING THE CREATION OF A MEMORY CELLxe2x80x9d Ser. No. 09/627,567, and xe2x80x9cUSE OF AN ETCH TO ROUND THE EDGES OF A RESIST MASK DURING THE CREATION OF A MEMORY CELLxe2x80x9d Ser. No. 09/668,051, both cases filed on even date herewith.
1. Field of the Invention
This invention relates generally to non-volatile memory devices. In particular, the present invention relates to a method and process for manufacturing a non-volatile memory device.
2. Background of the Invention
Non-volatile memory devices are currently in widespread use in electronic components that require the retention of information when electrical power is terminated. Non-volatile memory devices include read-only-memory (ROM), programmable-read-only memory (PROM), erasable-programmable-read-only memory (EPROM), and electrically-erasable-programmable-read-only-memory (EEPROM) devices. EEPROM devices differ from other non-volatile memory devices in that they can be electrically programmed and erased. Flash EEPROM devices are similar to EEPROM devices in that memory cells can be programmed and erased electrically. However, Flash EEPROM devices enable the erasing of all memory cells in the device using a single electrical current pulse.
Typically, an EEPROM device includes a floating-gate electrode upon which electrical charge is stored. The floating-gate electrode overlies a channel region residing between source and drain regions in a semiconductor substrate. The floating-gate electrode together with the source and drain regions forms an enhancement transistor. By storing electrical charge on the floating-gate electrode, the threshold voltage of the enhancement transistor is brought to a relatively high value. Correspondingly, when charge is removed from the floating-gate electrode, the threshold voltage of the enhancement transistor is brought to a relatively low value. The threshold level of the enhancement transistor determines the current flow through the transistor when the transistor is turned on by the application of appropriate voltages to the gate and drain. When the threshold voltage is high, no current will flow through the transistor, which is defined as a logic 0 state. Correspondingly, when the threshold voltage is low, current will flow through the transistor, which is defined as a logic 1 state. Data resides in a certain logic state on the floating-gate electrode. During a read operation, selected data from a selected floating-gate electrode can be output to an external communication unit using a bit-line.
In a flash EEPROM device, electrons are transferred to a floating-gate electrode through a dielectric layer overlying the channel region of the enhancement transistor. The electron transfer is initiated by either hot electron injection, or by Fowler-Nordheim tunneling. In either electron transfer mechanism, a voltage potential is applied to the floating-gate by an overlying control-gate electrode. The control-gate electrode is capacitively coupled to the floating-gate electrode, such that a voltage applied on the control-gate electrode is coupled to the floating-gateelectrode. The flash EEPROM device is programmed by applying a high positive voltage to the control-gate electrode, and a lower positive voltage to the drain region, which transfers electrons from the channel region to the floating-gate electrode. The flash EEPROM device is erased by grounding the control-gate electrode and applying a high positive voltage through either the source or drain region of the enhancement transistor. Under erase voltage conditions, electrons are removed from the floating-gate electrode and transferred into either the source or drain regions in the semiconductor substrate.
Product development efforts in EEPROM device technology have focused on increasing the programming speed, lowering programming and reading voltages, increasing data retention time, reducing cell erasure times and reducing cell dimensions. Many of the foregoing research goals can be addressed through development of materials and processes for the fabrication of the floating-gate electrode. Recently, development efforts have focused on dielectric materials for fabrication of the floating-gate electrode. Silicon nitride in combination with silicon dioxide is known to provide satisfactory dielectric separation between the control-gate electrode and the channel region of the enhancement transistor, while possessing electrical characteristics sufficient to store electrical charge.
One important dielectric material for the fabrication of the floating-gate electrode is an oxide-nitride-oxide (ONO) layer. During programming, electrical charge is transferred from the substrate to the silicon nitride layer in the ONO layer. Voltages are applied to the gate and drain creating vertical and lateral electric fields, which accelerate the electrons along the length of the channel. As the electrons move along the channel, some of them gain sufficient energy to jump over the potential barrier of the bottom silicon dioxide layer and become trapped in the silicon nitride layer. Electrons are trapped near the drain region because the electric fields are the strongest near the drain. Reversing the potentials applied to the source and drain will cause electrons to travel along the channel in the opposite direction and be injected into the silicon nitride layer near the source region. Because silicon nitride is not electrically conductive, the charge introduced into the silicon nitride layer tends to remain localized. Accordingly, depending upon the application of voltage potentials, electrical charge can be stored in regions within a single continuous silicon nitride layer.
Non-volatile memory designers have taken advantage of the localized nature of electron storage within a silicon nitride layer and have designed memory devices that utilize two regions of stored charge within an ONO layer. This type of non-volatile memory device is known as a two-bit EEPROM. The two-bit EEPROM is capable of storing twice as much information as a conventional EEPROM in a memory array of equal size. A left and right bit is stored in physically different areas of the silicon nitride layer, near left and right regions of each memory cell. Programming methods are then used that enable two-bits to be programmed and read simultaneously. The two-bits of the memory cell can be individually erased by applying suitable erase voltages to the gate and to either the source or drain regions.
While the recent advances in EEPROM technology have enabled memory designers to double the memory capacity of EEPROM arrays using two-bit data storage, numerous challenges exist in the fabrication of material layers within these devices. In particular, fabricating the p-type and n-type regions within a memory cell presents several challenges. Sometimes, in the fabrication of a memory cell, an ONO layer is formed having a first silicon dioxide layer overlying the semiconductor substrate, a silicon nitride layer overlying the first silicon dioxide layer, and a second silicon dioxide layer overlying the silicon nitride layer. A layer of photo resist is then spun on the ONO layer. The photoresist is patterned into a resist mask and the semiconductor substrate is doped with a p-type dopant such as boron using ion implantation at a large angle of incidence relative to the principal surface of the semiconductor substrate to allow the p-type implant to be located away from a subsequent n-type dopant. The wafer is then rotated 180xc2x0 and the semiconductor substrate is doped a second time with a p-type dopant using ion implantation at a large angle of incidence relative to the principal surface of the semiconductor substrate. Doping the semiconductor substrate with a p-type dopant creates p-type regions. The semiconductor substrate is then doped with an n-type dopant such as arsenic using ion implantation at an angle substantially normal to the principal surface of the semiconductor substrate. Doping the semiconductor substrate with n-type dopants creates n-type regions. Typically, the ONO layer is etched before the semiconductor substrate is doped with n-type dopants in order to make the implant of n-type dopants a more controlled implant. Once the n-type dopants have been implanted in the semiconductor substrate, the resist mask is stripped and cleaned from the ONO layer and a bit-line oxide region is thermally grown onto the semiconductor substrate.
There are several problems that occur with the above-described prior art method for fabricating a memory cell. One problem is that the resist mask has to meet two conflicting requirements: the resist mask has to be thin enough to accommodate the large angle of incidence of the p-type implant, and yet the resist mask has to be thick enough to withstand the n-type implant. If the resist mask is too thick, the p-type implant must be made with a smaller angle of incidence, however if the resist mask is too thin the n-type implant cannot be made at all because the resist mask would have been too heavily degraded. Accordingly, advances in memory cell fabrication technology are necessary to insure patterning of high density memory cells used in two-bit EEPROM devices.
The present invention is for a process for fabricating a memory cell in a non-volatile memory device, preferably in a two-bit EEPROM device. Fabrication of a two-bit EEPROM device having a memory cell requires the formation of p-type regions and n-type regions with good critical dimension control. This is because proper functionality of the two-bit EEPROM device during a programming operation requires voltages to be applied to the p-type regions and n-type regions. In particular, the p-type regions must be positioned at the edges of the ONO layer for fabrication of high density devices. However, fabrication of high density devices with p-type regions positioned at the edges of the ONO layer is hard to obtain due to the limitations of the resist mask. By fabricating a high quality memory cell using a resist flow operation, a high-density two-bit EEPROM device with good critical dimensions control can be manufactured.
In one form, a process for fabricating a memory cell includes providing a semiconductor substrate and forming an ONO layer over the semiconductor substrate. A layer of photoresist is then deposited overlying the ONO layer and patterned into a resist mask. The resist mask is thick enough to withstand an n-type implant. Preferably, the ONO layer is etched before the semiconductor substrate is doped with n-type dopants in order to make the implant of n-type dopants a more controlled implant, however, the ONO layer may be etched after the semiconductor substrate is doped with n-type dopants. The semiconductor substrate is then doped with an n-type dopant such as arsenic, preferably by using ion implantation. The doping of the semiconductor substrate with an n-type dopant causes n-type regions to form in the semiconductor substrate. Preferably, the n-type implant is a direct implant, which is an implant at an angle substantially normal with respect to the principal surface of the semiconductor surface.
After doping the semiconductor substrate with n-type dopants, a resist flow operation is performed on the semiconductor substrate by placing the semiconductor substrate in an oven. The resist flow operation thins down the resist mask and causes the corners of the resist mask to become rounded. Once the resist flow operation is performed, the semiconductor substrate is doped with p-type dopants such as boron, preferably by using ion implantation. The p-type implant is an angled implant, which is an implant at an angle substantially acute with respect to the principal surface of the semiconductor substrate. The doping of the semiconductor substrate with p-type dopants causes p-type regions to form in the semiconductor substrate. After doping the semiconductor substrate with p-type dopants the resist mask is removed and the bit-line oxide region is formed. The rounded corners and thinness of the resist mask allow for a more angled p-type implant. The more angled p-type implant allows for the fabrication of a memory cell having p-type regions positioned at the edges of the ONO layer.